from Hacker News

Intel-Micron Share Additional Details of Their 3D NAND

by Justen on 3/27/15, 2:27 PM with 5 comments

• by jjoonathan on 3/27/15, 5:46 PM

  Speaking of the HDD->SDD transition, is anyone familiar enough with SRAM and DRAM design/fab to comment on why we haven't seen a similar transition with memory? 60ns latency on a 4GHz processor = ouch!

  I'm aware that SRAM is 3-6x less dense, but it isn't uncommon these days to see people with >3x the DRAM they need, so this doesn't strike me as a terribly convincing justification.

  I'm also aware that $/GB is insanely high for on-CPU SRAM, but that would also be the case for on-CPU DRAM, which is why DRAM is typically put on a separate die so that its process can be optimized independently. Does the SRAM process just not optimize as well? Does it have insane power/heat requirements? What goes wrong?

  Or (puts on tinfoil hat) is JEDEC full of people who design DRAM memory controllers for a living?