from Hacker News

VHDL Verification Course

by nammi on 4/19/14, 5:13 AM with 11 comments

• by oflordal on 4/19/14, 6:31 AM

  This is quite dated from a modern chip development perspective. If you are interested in learning more of where the industry is today on functional verification look at things like SystemVerilog and Contrained random verification. Things are moving to use libraries/methodologies on top of SystemVerilog like UVM (or OVM and VMM before it). Doulous has quite good introductions: https://www.doulos.com/knowhow/sysverilog/uvm/

• by tonglil on 4/19/14, 7:06 AM

  Oh boy VHDL, got my final on that on Tuesday. Nice to have learned it, but personally I appreciate the abstraction provided, by even C.

  What is the applicability of this skill in the modern chip development industry?

• by breton on 4/19/14, 9:44 AM

  The course assumes some knowledge of VHDL. Could somebody suggest a course/book on Verilog or VHDL for beginners?