by broken_broken_ on 2/18/25, 8:48 AM with 20 comments
by molenzwiebel on 2/18/25, 7:46 PM
by ack_complete on 2/18/25, 8:07 PM
The comments in the SSE2 version are a bit odd as it references MMX, and the Pentium M and Efficeon CPUs. Those CPUs are ancient -- 2003/2004 era. The vectorized code you have also uses SSE2 and not MMX, which is important since SSE2 is double the width and has different performance characteristics from MMX. IIRC, Intel CPUs didn't start supporting SHA until ~2019 with Ice Lake, so the target for non-hardware-accelerated vectorized SHA1 for Intel CPUs would be mostly Skylake-based.
by bean-weevil on 2/18/25, 2:26 PM
by tvbusy on 2/18/25, 9:35 PM
by Neywiny on 2/19/25, 1:56 AM