from Hacker News

Verilog to Minecraft Redstone Synthesizer

by parkertomatoes on 11/24/20, 6:12 AM with 12 comments

  • by unsigner on 11/24/20, 8:20 AM

    This is so Greg Egan.

    (An Australian sci-fi author who likes to layer realities computed/simulated on top of each other - give Diaspora or Permutation City if it sounds like your cup of tea.)

  • by itsame1 on 11/24/20, 10:22 AM

    See also: https://github.com/google/minetest_pnr

    Similar project but for minetest (open source minecraft clone)

  • by cmrdporcupine on 11/24/20, 10:14 AM

    This is very cool, and I wonder if I could work something like this into a way to teach my (10 year old) son the basics of digital logic.

    In his case I suspect the full syntax of Verilog would be overkill and just add confusion, though. A simpler subset without modules and with only continuous assignment would be ideal.

    Gears turning.

  • by lainga on 11/24/20, 5:52 PM

    While it may produce the right logic tables, there's a lot of room for optimisation. I'd like to see that. For instance the two repeaters near the end of the 4th trace from bottom in the example image []: obviously they have just been placed at element boundaries to ensure signal propagation, but each one induces a 1-tick delay in that propagation. And you don't need 2 of them so close together, as it seems there's another repeater less than 16 blocks away from the first one. IMO the real art of making gates in MC is twisting them back on themselves so you get as few ticks of delay as possible.

    [] https://raw.githubusercontent.com/itsFrank/MinecraftHDL/mast...