by herogreen on 6/13/20, 9:59 PM with 79 comments
by herogreen on 6/13/20, 10:12 PM
by haberman on 6/14/20, 12:28 AM
A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables.
But the instruction encoding is much more irregular than I expected: https://github.com/ucb-bar/riscv-sodor/blob/master/src/commo...
In particular:
- The bit patterns allocated to the simplest instructions
(eg. rv32i) seem random. Why not allocate starting from zero
to allow dense jump tables?
- I can't make any sense of the groupings. A bunch of instructions
have 0b1100011 in the lowest bits, do these instructions have
something in common?
I assume there is some rhyme and reason to all this? Where is this explained?by q3k on 6/13/20, 10:37 PM
Also worth noting, that you can use a fully open source flow (Yoys + nextpnr + prjtrellis) for this FPGA family. Here's a repository I made that shows a basic blinky for an ULX3S: https://github.com/q3k/ulx3s-foss-blinky/
by tyingq on 6/13/20, 11:35 PM
Edit: After a lot of back and forth, perhaps this is a good intro: https://hackaday.com/2019/01/14/ulx3s-an-open-source-lattice...
by bloopernova on 6/13/20, 11:03 PM
by ngcc_hk on 6/14/20, 12:20 AM
Just placed an order : https://www.crowdsupply.com/radiona/ulx3s
by wolrah on 6/14/20, 2:48 AM
From my rudimentary understanding it looks like this doesn't have a hard CPU and has a smaller FPGA, so I'm guessing we have a fair bit of "open hardware tax" at play here too.
by pjmlp on 6/14/20, 7:06 AM
by b1ackb0x on 6/14/20, 5:44 AM
by sitzkrieg on 6/13/20, 11:19 PM
by gre on 6/14/20, 12:34 AM
by lihaciudaniel on 6/14/20, 3:31 PM
by johan_larson on 6/13/20, 11:37 PM
$150
by rasz on 6/13/20, 11:04 PM