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Show HN: detecting cache latency inside a Web browser

by Marat_Dukhan on 1/6/18, 7:52 AM with 47 comments

• by Marat_Dukhan on 1/6/18, 11:03 AM

  Author here. I made this demo and a related matrix-matrix multiplication demo [1] back in 2015 for Robert van de Geijn's Linear Algebra: Foundations to Frontiers MOOC class [2]. In the light of Spectre attack and recent browsers' changes to reduce precision of timers, I remembered of this project, and decided to check if it still works now, 3 years later. Surprisingly, it still works well!

  The source code is available on GitHub [3].

  [1] https://maratyszcza.github.io/laff-demos/dgemm.html

  [2] https://www.edx.org/course/linear-algebra-foundations-fronti...

  [3] https://github.com/Maratyszcza/laff-demos

• by kaoD on 1/6/18, 10:48 AM

  On my pretty outdated Core 2 Duo Q9300: https://i.imgur.com/HQXm5FU.png

  The CPU is advertised as 6 MB L2 cache[0] but it has "L1 = 4 x 32 KB 8-way set associative data caches and L2 = 2 x 3 MB 12-way set associative caches (each L2 cache is shared between 2 cores)"[1].

  You can clearly see the constant time access to L1 cache up to 32KB. Then grows to (linear?) access time up to 2MB (where it still fits in one of the L2 caches) and then again a different (log-like?) function from there on.

  This is really neat.

  [0] https://ark.intel.com/products/33922/Intel-Core2-Quad-Proces...

  [1] http://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Quad%2...

• by esnard on 1/6/18, 12:42 PM

  Somewhat related: using the cache latency to estimate the CPU cache size. https://fromwhenceitca.me/cache_size/cache_size.html

• by jacquesm on 1/6/18, 11:40 AM

  So, who thought it was a great idea again to use a mechanism intended for document transfer to run unsigned, unaudited code on just about every client in the world?

• by Sephr on 1/6/18, 11:20 AM

  This is similar to how I detected total CPU cores in 2013 to implement navigator.hardwareConcurrency: https://eligrey.com/blog/cpu-core-estimation-with-javascript...

• by laCour on 1/7/18, 1:48 AM

  i5-4690K (L1 4x32KB; L2 4x256KB; L3 6MB): https://i.imgur.com/FUs1isW.png

  LG v30 (L2 2MB): https://i.imgur.com/q5R3bLY.png

• by polyfemos on 1/10/18, 11:36 PM

  And with the latest iOS 11.2.2, this (admittedly cool) piece of code no longer works.

  Still works on the latest MacOS (10.13.2) though.

• by mherrmann on 1/6/18, 10:07 AM

  On my OnePlus X Android phone: https://imgur.com/a/C1hb7

• by Yetanfou on 1/6/18, 12:52 PM

  Thinkpad T42p with Pentium M 1.8GHz, 2MB L2 cache

  https://imgur.com/agxy8e7

• by Mister_Snuggles on 1/6/18, 7:04 PM

  I'd like to see some text explaining what I'm looking at.

  Based on the title, it's something to do with cache latency, but that doesn't really help me. What exactly is it measuring? How does it perform this measurement? What are the limitations of this technique? What are the wider implications of this? What uses does it have, both potentially nefarious ones and potentially beneficial ones?

• by yeukhon on 1/6/18, 11:16 AM

  Is there plan to collect this data voluntarily? Would be interesting to see the different percentiles

• by chrisper on 1/6/18, 9:41 AM

  Is that Ram only or also L1 etc. caches?