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Create Your Own CPU on an FPGA

by kardashev on 8/20/15, 2:48 AM with 20 comments

  • by farresito on 8/20/15, 10:03 AM

    Some guy started a series some weeks ago on designing a CPU for an FPGA: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...

    For those interested in a more complex processor, RISC-V seems to be a processor on par with ARM in terms of features: http://riscv.org/

  • by kardashev on 8/20/15, 2:05 PM

    Does anyone have knowledge about the comparison of different FPGA boards?

    I've seen the Mojo v3 from Embedded Micro, the Papilio line of dev boards, and the miniSpartan6+ from Scarab Hardware.

    It looks like all these dev boards are pretty similar since they use almost identical xilinx chips. Ideally, I'd like to find a board for which there is a robust community, good support, lots of examples, and has enough capacity/performance to take on more complicated projects with increased learning/skill.

    I'm leaning towards the Mojo v3 board, since it seems very easy and has shields to expand capability, but does anyone have any experience, recommendations, or "I wish I had known..." stories for FPGA development?

  • by pjc50 on 8/20/15, 9:19 AM

    ... using the "Lucid" HDL, which at first glance seems like a de-crufted Verilog.

  • by zeusk on 8/20/15, 12:55 PM

    I'll just leave this here: https://github.com/zeusk/CS242

    I did this during my sophomore year, didn't care much about implementing a proper memory implementation as that was way beyond the scope of our course.

  • by scottmwinters on 8/20/15, 12:20 PM

    Every Computer Engineering undergrad is rejoicing somebody just did their project for them.

  • by m3talridl3y on 8/20/15, 4:40 PM

    Does anyone have any tips on determining if a given CPU core will fit onto a given FPGA? Most of the boards in the hobbyist price range seem kinda ... underwhelming.

  • by alain94040 on 8/20/15, 4:12 PM

    No discussion of CPU design is complete without trying to run your design as fast as possible. That's how people discovered that pipelining is good, and a flat implementation (such as the one in that code) is slow.